1. Field of the Invention
This invention relates to a semiconductor chip, a semiconductor package and to a method of assembling a semiconductor package, and to a method of producing a semiconductor chip.
2. Discussion of Related Art
The term "frontside" of a semiconductor wafer or semiconductor chip, as used herein, denotes the side of the semiconductor wafer or semiconductor chip which carries integrated circuitry, and the term "backside", as used herein, denotes a side of the semiconductor wafer or the semiconductor chip opposing the frontside.
A semiconductor package usually includes a package substrate and a semiconductor chip located on or in the package substrate. Semiconductor chips are commonly produced with C4 (controlled collapse chip connect) solder connections, on a frontside thereof, for purposes of electrically contacting the integrated circuit on the frontside of the chip to contact pads on the package substrate, electronically connecting the chip to the package substrate. An epoxy is typically introduced under capillary action into a space between the semiconductor chip and the package substrate and is subsequently cured. The epoxy acts to bond the semiconductor chip to the package substrate and to protect the C4 solder connections during the temperature cycling it will experience during the product's lifetime.
The semiconductor chip is made primarily of silicon which has a coefficient of thermal expansion (CTE) of about 3.3 ppm/.degree. C. (parts per million per .degree. C.). In the past, the package substrate was generally made of a ceramic material, which has a coefficient of thermal expansion that is typically below 6 ppm/.degree. C. During heating or cooling of the semiconductor package, the coefficients of thermal expansion of the semiconductor chip and the ceramic package substrate, respectively, were not of a magnitude which caused substantial deformation caused by stress buildup in the package.
Ceramic has a relatively high dielectric constant which causes stray capacitance to build up within the package substrate, resulting in resistance-capacitance (RC) delay. The move in recent years has therefore been away from ceramic as a package substrate material to alternative materials, such as plastics or other organic materials, which have lower dielectric constants. A problem with these alternative materials, on the other hand, is that they usually have relatively high coefficients of thermal expansion, compared to the coefficient of thermal expansion of the semiconductor chip. Plastic substrates often have coefficients of thermal expansion on the order of 17 ppm/.degree. C. Heating or cooling of the semiconductor package thus results in substantial stress and deformation in the semiconductor chip.
As discussed above and in reference to FIG. 1, an epoxy material 102, generally a glass-filled epoxy, is provided within the space between the semiconductor chip 104 and the package substrate 106 and cured. The step of curing the epoxy involves elevating the temperature of the semiconductor package 108 to a given temperature for a specific period of time. Once the curing procedure is complete, the semiconductor package is then cooled to ambient temperature. FIG. 1 illustrates an organic semiconductor package 108 after being cured and cooled to ambient temperature. Since the CTE of the organic package substrate 106 is much greater than the CTE of the semiconductor chip 104, the package substrate 106 tends to reduce in size during cooling at a much faster rate than the semiconductor chip 104. This causes the semiconductor package 108 to warp in a manner that results in an outward bowing or bending of the semiconductor chip 104.
Bending or bowing of the semiconductor chip is problematic, in that it induces greater stresses along the backside 109 of the semiconductor chip. Surface defects 114, such as nicks and scratches, are generally present along the backside edges of the semiconductor chip as a result of the sawing procedure used to separate the chip from a wafer. Since stress concentrations along the backside edge of the chip are particularly high, bending of the chip causes the cracks to develop rapidly into longer cracks which propagate through the semiconductor chip. Propagation of the defects can cause severe damage to the chip, and can eventually cut through active circuitry on a frontside 111 of the semiconductor chip, resulting in electrical failure of the semiconductor chip.
The difference in the CTE of the semiconductor chip 104 and organic package substrate 106 also produces tensile stresses 110 and sheer stresses 112 that act upon the epoxy interface 102 that joins the two components. These stresses tend to delaminate the epoxy interface material from the semiconductor chip, particularly at the frontside edges of the chip where higher stress concentrations reside.